1. Field of the Invention
The invention relates to a method for polishing both sides of a semiconductor wafer, in particular, for polishing silicon wafers of the next technology generations, primarily wafers which have a diameter of 450 mm.
2. Background Art
At present, polished or epitaxially processed semiconductor wafers with a diameter of 300 mm are used for the most demanding applications in the electronics industry. Silicon wafers with diameters of 200 mm are gradually being replaced by 300 mm wafers.
An essential reason why the electronics industry desires larger substrates for the production of their components, whether microprocessors or memory chips, resides in the enormous economic advantage which they promise. In the semiconductor industry it has for a long time been customary to focus on the available substrate area, or in other words to consider how great a number of components, i.e. logic chips or memory chips, can be accommodated on an individual substrate. This is related to the fact that a multiplicity of the component manufacturer's processing steps are aimed at the entire substrate, but there are also the individual steps for structuring the substrates i.e. producing the component structures which subsequently lead to the individual chips, and therefore the production costs for both groups of processing steps are very particularly determined by the substrate size. The substrate size influences the production costs per component to a very considerable extent, and is therefore of immense economic importance.
However increasing the substrate diameter entails great and sometimes entirely new, hitherto unknown technical problems. All the processing steps, whether they are purely mechanical (sawing, grinding, lapping), chemical (etching, cleaning) or chemical-mechanical in nature (polishing) as well as the thermal processes (epitaxy, annealing), require thorough revision, in particular with respect to the machines and systems (equipment) used for them.
WO 99/55491 A1 describes a two-stage polishing method with a first “fixed abrasive polishing” (“FAP”) polishing step and a subsequent second CMP polishing step. For CMP, the polishing pad does not contain fixed abrasive. As in a double-sided polishing (“DSP”) step, abrasive is introduced here in the form of a suspension between the semiconductor wafer and the polishing pad. Such a two-stage polishing method is used, in particular, to remove scratches which the FAP step has left behind on the polished surface of the substrate.
EP 1 717 001 A1 is an example of FAP steps also being used for the polishing of semiconductor wafers, on whose surface component structures have not yet been formed. The polishing of such semiconductor wafers is primarily aimed at producing at least one side surface which is particularly flat, and which has the smallest possible microroughness and nanotopography.
US 2002/00609967 A1 relates to CMP methods for planarizing topographical surfaces during the production of electronic components. The primary aim is to alleviate the disadvantage of comparatively low removal rates when using FAP polishing pads. A sequence of polishing steps is proposed, in which polishing is carried out first with an FAP pad in combination with a polishing agent suspension and subsequently with an FAP pad in conjunction with a polishing agent solution. The sequence of steps is deliberately selected in order to increase the removal rate. The polishing of wafers made of a material with a homogeneous composition, for example silicon wafers, is not disclosed therein.
Likewise, WO 03/074228 A1 also discloses a method for planarizing topographical surfaces during the production of electronic components. Here, the focus of the invention resides in the endpoint detection of the CMP method. As is known, endpoint detection involves ending the polishing and therefore the material removal promptly before it causes the removal of regions which are not in fact intended to be polished. To this end, a two-stage method is proposed for polishing a copper layer. In the first step polishing is carried out with an FAP polishing pad, in which case the polishing agent optionally may or may not contain free abrasive particles. In the second polishing step however, in which polishing is likewise carried out with an FAP pad, the use of a polishing agent with free abrasive particles is essential.
Unpublished German Patent Application 102 007 035 266, describes a method for polishing a substrate made of semiconductor material, comprising two polishing steps of the FAP type which differ from one another in that a polishing agent suspension containing fixed abrasive as a solid substance is introduced between the substrate and the polishing pad in one polishing step, while in the second polishing step the polishing agent suspension is replaced by a polishing agent solution which is free of solids.
All the methods known in the prior art have a crucial disadvantage with respect to stock polishing, which includes conventional double-sided polishing methods and the FAP polishing method. Both sides of the semiconductor wafer are polished simultaneously, which leads to an unfavorable edge geometry, in conventional double-sided polishing a so-called “edge roll-off” i.e. an edge reduction relative to the thickness of the semiconductor wafer. Experiments have shown that this problem is even further exacerbated when polishing wafers with larger diameters, i.e. for example the aforementioned wafers with a 450 mm diameter. The larger substrates entail an increase in the differential polishing removal at the wafer edge and in the remaining region of the wafer, so that edge roll-off is even more pronounced.
This is problematic in particular owing to the fact that according to the internationally agreed so-called Roadmap (ITRS, “International Technology Roadmap for Semiconductors”, chapter “Front End Processes”), the manufacturers of semiconductor wafers are required to increase the area of the wafers which can be used for producing components and reduce the so-called “edge exclusion” which is not available for components.
While an edge exclusion of 2 mm is currently considered to be acceptable, initially this size will become more difficult to achieve in future years owing to the increase in the wafer diameter to 450 mm, and subsequently it will even be reduced to 1 mm. This will only be accomplished by significantly reducing the edge roll-off. It would be desirable to eliminate edge roll-off entirely.
Another characteristic, which is subject to ever more stringent requirements according to the ITRS Roadmap, is the nanotopography of the semiconductor wafer. The nanotopography is conventionally expressed as a height variation PV (=“peak to valley”), based on square measurement windows with an area of 2 mm×2 mm. Here again, it was found long ago that the previous polishing methods are not sufficient to satisfy the increased requirements of larger semiconductor wafers.
Lastly, besides the edge geometry and the nanotopography, the global and local planarities are also of crucial importance for making the next and subsequent technology generations possible. One particularly critical property is the local planarity or local geometry of the semiconductor wafer on its frontside. Modern stepper technology demands optimal local planarities in subregions of the frontside of the semiconductor wafer, expressed for example as SFQR (“site front-surface referenced least squares/range”=magnitude of the positive and negative deviations from a frontside, defined by least squares minimization, for a component surface (measurement window, “site”) of defined dimension). The maximum local planarity value SFQRmax indicates the highest SFQR value for the component surfaces taken into account on a semiconductor wafer.
The maximum local planarity value is conventionally determined by taking an edge exclusion of 2 mm into account. An area on a semiconductor wafer inside a nominal edge exclusion is conventionally referred to as “fixed quality area”, abbreviated to FQA. Those sites which lie with a part of their area outside the FQA, but whose centers lie inside the FQA, are referred to as “partial sites”.
A generally acknowledged rule of thumb states that the SFQRmax value of a semiconductor wafer must be equal to or less than the line width possible on this semiconductor wafer for semiconductor components to be produced on it. Exceeding this value leads to focusing problems for the stepper, and therefore to loss of the relevant component.
Currently, the semiconductor wafers available on the market correspond to the 45 nm technology generation (line width=45 nm) which is gradually being replaced by the already developed 32 nm technology, and to this extent the component manufacturers are also gradually changing their device processes accordingly. The 22 nm technology generation, which will follow this, is already in development. It has been found that the conventional polishing methods are indeed not sufficient for satisfying the requirements of the 22 nm design rule.